Current sampling 1: when in the PWM period

Which instant of the PWM period did 7b's U reading of 32990 come from? TIM1 counts 0 → 6000 → 0 centre-aligned at 240 MHz, one period every 50 µs; channel 4 at compare value 1 fires TRGO 4 ns after every valley, the three ADCs sample together, and only ADC1 raises the interrupt. The valley is farthest from every switching edge (the Y01 schematics show the shunts inline in each phase, read by an INA240A1), and the ripple crosses its average: 0.28 A peak to peak in the model, 0.02 mA off at the valley. The 90% duty cap (inferred: it lets the upper switch's bootstrap supply recharge) keeps the lower switch on for at least 2.5 µs; new compare values wait for the next peak. Compare values come from real runs (the board build and the BSP bench); the timing pictures are worked out from the registers.