Four gates 4: one tick late

Gate 4, hw_ready_state, opens at 1102.45 ms, yet PP only starts at 1102.55 ms. One position tick, opened up: the bench renames the calls in motor_ctl_loop.c at compile time (the source is unchanged) and logs every call in order with the values it left behind. A tick has four steps: encoder in → application layer (AppRun) → control layer → outputs and hw_ready_state. AppRun reads in step 2, hw_ready_state is written in step 4, so that tick reads 0, like a teacher taking the register before a late student signs in; the control layer's ModeRun likewise. The command is not late: the planner writes 39228 in step 2, step 3 of the same tick turns it into an iq target of 0.0118 A, and 50 µs later the compare values move to 3296/3297/3305. The rule: a value written later in a tick is seen on the next tick. All from real call traces.